A Novel AES VLSI Architecture with Fully-Sub Pipelined Structure for High Throughput and Area Efficiency

This paper presents novel high-speed architectures for the hardware implementation of the Advanced Encryption Standard (AES) algorithm. Unlike previous works which rely on look-up tables to implement the SubBytes and InvSubBytes transformations of the AES algorithm, the proposed design employs combinational logic only. As a direct consequence, the unbreakable delay incurred by look-up tables in the conventional approaches is eliminated, and the advantage of subpipelining can be further explored. Furthermore,composite field arithmetic is employed to reduce the area requirements, and different implementations for the inversion in subfield (24) are compared. The subkeys, required for each round of the Rijndael algorithm, are generated in real-time by the keyscheduler module by expanding the initial secret key, thus reducing the amount of storage for buffering. Moreover, a novel architecture was proposed for the fully sub-pipelining is used after each standard round, and sub-pipelined with in the round states, so throughput was increased double to any pipelined architecture. This AES design was implemented using Verilog HDL and synthesized using TSMC’s 90 nm standard cell library with RTL Compiler, and physical design implementation was done using SOC Encounter and achieved the through put of 38. 4 Gbps after detailed routing.