Hardware Implementation of CRC Architectures

This paper deals with Design and Hardware Implementation of Cyclic Redundancy Check (CRC) with the help of HDL codes.  As we know that CRC codes ensure data integrity for high speed serial links such as fiber channel and hence these codes are used for high speed communication systems. In practice, CRC codes are implemented serially which consumes 16-clock cycles in case of 16-bit CRC code and 32 clock cycles for 32-bit code. This paper provides a methodology for implementing CRC codes concurrently, so as to reduce the number of clock cycles. In this paper, we have designed CRC algorithm using Very High Speed Integrated, Hardware Description Language(VHDL) and code is written in Xilinx I.S.E 7.1i version, synthesized on Xilinx Synthesis Tool (XST). Implemented on Spartan-III FPGA.

FPGA implementation of such a prototype is finding its application in Error Detection and Correction in data communication, Ethernet Signature Analysis, and Radio Frequency Identification (RFID).