Power Optimization for Dual-Clock FIFO with Closedown Able and Reinstate Able Clock Domains

This paper implements a scalable, and power efficient dual-clock first-input first-out (FIFO) architecture which is useful for transferring data between modules operating in different clock domains. This architecture supports correct operation in applications where multiple clock cycles of latency exist between the data producer, FIFO, and the data consumer; and with arbitrary clock frequency changes, halting, and restarting in either or both clock domains. A dual port RAM is used as the storage element which increases memory density and improves FIFO size scalability. The architecture includes configurable logic to make it suitable for many environments, and also enables complete clock halting during idle times to achieve high energy efficiency. The address pointers are transformed to gray code representation before being passed across the clock boundary and these are then converted back to binary format in the clock domain. The skew control block which includes reconfigurable delays, is inserted to balance the timing between signals. The architecture demonstrated is implemented using verilog HDL and can be implemented to cell design using TSMC 180 nanometer. The design uses a globally asynchronous and locally synchronous (GALS) array of processors. This architecture achieves 620-MHz operation and 4.17-mW power dissipation while performing simultaneous FIFO READ and WRITE operations using TSMC 180nm technology. This dual-clock FIFO architecture is well suited for many dual-clock applications and achieves high energy efficiency, good scalability and area utilization, at high clock rates.