Design and Implementation of CRC Architecture Using Double-Edge Triggered Flip-Flop

The Cyclic redundancy check is an efficient error detection technique that is widely utilized in digital data communication, Ethernet, ATM and other fields such as data storage, data compression. In general, it is possible for CRC polynomials to detect all single-bit, double-bit and burst errors. Our paper presents the design and implementation of a programmable cyclic redundancy check (CRC) computation circuit architecture using Double Edge Triggered Flip-Flop, suitable for deployment in network related system-on-chips. DET flip-flop has been used, since it reduces the operating clock frequency to half and reduces the no. of clock cycles required for data transition compared to the use of D Flip-Flop. The architecture has been designed to be field programmable so that it is fully flexible in terms of polynomial deployment and input port width. The circuit also includes an embedded configuration controller that has a low reconfiguration time and hardware cost.