Power Computation Model of CMOS Based FPGA Used for Power Optimization

To avail a longer battery life is a major constraint in the area of digital circuit design where complexity increases as per the Moore’s law. With the evolution of CMOS technology, it was believed that power consumption problem has been solved because static power consumption is very low and designers where focusing mainly on performance and area. But with the reasonable increase of device density per unit area the power consumption becomes considerably high. This is absolutely true for FPGAs, where power consumption noticeably rises due to the increase in the clock frequency, chip area and the ability to be programmed. FPGAs formed by three different technologies such as pure CMOS, Pass transistors and SRAM based. It becomes very popular because it takes very less development time, instant prototyping and less back end process. Hence, power consumption estimation and then optimisation has become very important. Looking to these facts this paper will explain the total power consumption model for CMOS based FPGAs because the power estimation is basic requirement for power optimized implementation on FPGAs.