Implementation of 90nm Technology Multi Test Pattern Sequence LFSR for Fault Testing

The increasing growth of sub-micron technology has resulted in the difficulty of VLSI testing. Test and design for testability are recognized today as critical to a successful design. BIST is a design technique that allows a circuit to test itself. The technique can provide shorter test time compared to an externally applied test and allows the use of low-cost test equipment during all stages of production. Due to the randomness properties of Linear Feedback Shift Registers (LFSR), this requires very little hardware overhead. However conventional LFSR fall short in fault coverage. In order to improve the fault coverage we introduce an improved LFSR called Multi Test Pattern Sequence LFSR (MTPS LFSR). In this paper the structure of this improvised LFSR is described. This paper also focuses on the implementation of low power MTPSLFSR using various CMOS logics. This paper discusses architectures in terms of the hardware implementation, using pass transistor logic CMOS layout and power consumption, using 90nm CMOS layout Technology. Along with this it also explains about fault coverage improvement by using MTPS LFSR.