An Extended March Test Algorithm Using for Fault Detection and Repair

In these paper implementing fault detection and repair of word redundancy MBISR (Memory Built In Self Repair) using March SS and march RAW algorithms. A new micro coded BIST architecture is presented here which is capable of employing new test algorithms like March SS and March RAW that have been developed for coverage of some recently developed static and dynamic fault models. The same hardware has been used to implement other new March algorithms. This requires just changing the Instruction storage unit, or the instruction codes and sequence inside the instruction storage unit. The instruction storage unit is used to store predetermined test pattern. The simulation results have shown that the micro-coded MBIST architecture described here is an effective testing method to test embedded memories as it provides a flexible approach and better fault coverage. Just as March SS, any other new march algorithm can also be implemented using the same BIST hardware by changing the instructions in the microcode storage unit, without the need to redesign the entire circuitry. The word redundancy uses spare words in place of spare rows and columns. This repair mechanism avoids lengthy redundancy calculations as suggested by some other authors in their works as it stores faulty location addresses immediately supporting on-the-fly fault repair. Moreover, it can be interfaced easily with existing MBIST logic.