Design of 10 Bit 60 MSPS Low Power Pipelined ADC

Among various ADC architectures, a pipelined ADC is suitable for high-speed, high-resolution, and low-power operation. The presented architecture utilizes a combination of two power reduction techniques such as split capacitor Correlated Double sampling (SC-CDS) technique and op-amp sharing technique. Using this approach a 10 bit 60MSPS pipelined ADC has been designed in a 180nm CMOS technology. Also power comparison of 10-bit Pipelined ADC with Sample-and-hold-amplifier (SHA) and without SHA is also performed. Simulation results shows a power consumption of 15.7mW with SHA and 3.19mW without SHA from a 1.8V supply voltage using CADENCE software.