Design of ADC for ECG Applications using 0.18μM CMOS Technology

The necessity of wireless ECG transmission is increasing in day to day life. To transmit the ECG signal, the conversion of analog ECG to digital is more important and the same is achieved using analog to digital converters. This paper concentrates on the design of charge redistribution successive approximation type ADC in 180nm CMOS technology. This analog to digital converter is designed for the use of wireless medical ECG applications with the sampling rate of 5KS/s and 10 bit resolution for the input range of 10mv, since the ECG signal having very less amplitude. The principle used in this paper is charge redistribution adiabatic charging type digital to analog converter in the ADC circuit which consumes very less power. The regenerative comparator in the ADC also reduces the power consumption of the circuit. The digital output is collected from the SAR register which is constructed using flip-flops which can act as a ring counter. The SAR register gets the input from the regenerative comparator which is the error signal of the comparator from charge redistribution DAC and S&H. The whole circuit is driven by the clock input. This ADC will be more suitable for low frequency medical applications consuming 8.3μW at 1.2V supply voltage. Noise analysis is done and jitter noise is reduced.