Design and Implementation of 16-Point FFT Based on Radix-2 Algorithm using FPGA

FFT plays a very important role in real-time signal processing applications. This paper concentrates on the design of an FFT processor that computes 16-point FFT, based on Decimation-In-Domain (DIT), radix-2 algorithm. A codesign concept is used in which 16-point FFT is completed in a Xilinx Spartan-3 FPGA chip that contains MicroBlaze processor where the hardware is modeled by VHDL and the software is written in Impulse C. FPGA EDK hardware is used to simulate and synthesize the VHDL and Impulse C. A radix 2 FFT algorithm is designed using VHDL structural level modeling and this synthesizes and creates the bit file. The Impulse C helps to create the executable file in software flow side. The Xilinx Platform Studio (Embedded Development Kit – EDK) is used to control the FPGA and both the files (bit and executable) are loaded into the FPGA kit. The FFT inputs are fed to the FPGA via Xilinx Platform Studio and the FFT equivalent outputs are displayed in PC through UART. The synthesis results show that the computation for calculating 16-point FFT is efficient in terms of resource utilization and power consumption.