An Efficient System on Chip Interconnect Using Effective Bias Circuit

Continuous scaling down the transistor size causes the delay of local wires to decreases while delay of global wires remains the same. The current mode signaling (CMS) with effective bias circuit produce low power consumption over long on chip interconnect. This paper deals with variation tolerance with dynamic overdriving that produce less power consumption and proposed smart bias that increases the signal integrity through long distance communication. This proposed Smart bias is sensitive to both inter-die and intra-die variation. The CMS scheme and the proposed Scheme is tested using 0.18um technology.