Clock Power Reduction Using Multi-Bit Flip-Flop

The increasing demand for battery-powered and green-compliant applications has made power management a dominant factor in SoC design. To get maximum reduction in power various low-power techniques are considered. An algorithm has been proposed in which some flip-flops are replaced with fewer multi-bit flip-flop without affecting the performance. Mergable flip-flops are first identified and without affecting the performance flip-flops are replaced however replacement will change the location of some flip-flops leading to timing and capacity constraint. By replacement there will be maximum reduction in power counter and SRAM has been designed which reduces clock power by 15%.