Comparison of Leakage Current at Deep Sub Micron Technologies in CMOS Digital Circuit

High leakage current in Deep-Sub Micron (DSM) regimes is becoming a significant contributor to power dissipation of CMOS circuit parameters are reduced. This paper focusing on the leakage current which is highly dependent on potential applied on the transistors gate. That's why it can be said that input of the logic gate is able to control the leakage of the gate appropriately during run time of the device. Consider the input vector methodology to analyse NAND logic with 2 inputs using HSPICE simulator with BPTM technologies (i.e. 180nm, 130nm, 90nm, 65nm, 45nm) model. It gives the similar behaviour of leakage current with every technology models. Hench we can shift the logic gate input with its Minimum Leakage Vector (MLV) during run time of the device. Above technique is process parameter independent and there is no need of any extra power supply to reducing the leakage.