FPGA Implementation of Low Power Image Scaling Processor Using Bilinear Interpolation

VLSI architecture of resource efficient the image scaling processor is proposed in this project. The filter combining, hardware sharing, and reconfigurable techniques had been used to reduce hardware cost. This image Scaling Processor consists of a sharpening spatial filter, a clamp filter, bilinear and a nearest neighborhood interpolation. To reduce the blurring and aliasing artifacts produced by the bilinear interpolation, the sharpening spatial and clamp filters are added as prefilters. To minimize the memory buffers and computing resources for the proposed image processor design, a T-model and inversed T-model convolution kernels are created for realizing the sharpening spatial and clamp filters. Compared with previous low-complexity techniques, this architecture requires only a one-line-buffer memory. For achieve more quality images the orthogonal decoder is proposed. This proposed system is designed using verilog HDL, simulated using Modelsim Software and synthesized using Xilinx Project Navigator.