Networking and Communication Engineering

N. Kannaiya Raja ¹, K. Arulanandam ², R. Prabhu ³

Affiliations
1 CSE Department, Arulmigu Meenakshi Amman College of Engineering, Thiruvannamalai district, Near Kanchipuram, IN
2 CSE Department, Ganadipathy Tulsi’s Jain Engineering College, Vellore, IN
3 Arulmigu Meenakshi Amman College of Engineering, Thiruvannamalai District, Near Kanchipuram, IN

Abstract

Multi-pattern string matching remains a major performance bottleneck in network intrusion detection and anti-virus systems for high-speed deep packet inspection (DPI). Although Aho-Corasick deterministic finite automaton (AC- DFA) based solutions produce deterministic throughput and are widely used in today's DPI systems such as Snort and ClamAV, the high memory requirement of AC-DFA (due to the large number of state transitions in AC-DFA) inhibits efficient hardware implementation to achieve high performance.. Novel and scalable pipeline architecture for memory- efficient multi-pattern string matching is then presented. The architecture can be easily extended to support multi-character input per clock cycle by mapping a compressed AC-DFA onto multiple pipelines. In this paper the architecture to support enhanced multi-character input per clock cycle to achieve multiplicative throughput improvement. By using multi pipelining Now we can use the efficient architecture also available to support much larger pattern sets by using a limited number of external memory and also work done integrating proposed string matching architecture with DPI processing engine such packet header and other flags with regular expressing. Very fast regular expression matching is currently used here for applications searching for large pattern sets with increasingly faster data streams and minimize the through put by pipelining process and comparing him high level to reduce the state and minimize the throughput.

Keywords

Deep Packet Inspection, DFA, FPGA, Pipeline, String Matching.

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