Networking and Communication Engineering

Abstract

Nowadays, the current need consisting of implementing more and more complex systems imply the need of developing new methodologies to make the computer aided design (CAD) product reliable in order to improve time to market, study costs, reusability and reliability of the design process. The verification of analog and mixed signal designs is one of the major tasks in CAD. The need for new analogue synthesis techniques that would be able to support a future high-level mixed-signal synthesis environment is increasing along with the advancement in technology and the evolution of commercial requirements. The emergence of VHDL-AMS since 1999 has provided a platform which can form the basis for high-level analogue and mixed-signal synthesis systems. Many efforts are focused on the development of new methodologies to integrate the Top-Down hierarchical design flow in a synthesis environment using VHDL-AMS. This paper proposes a simulation platform useful for the simulation and the optimization of fractional-N Phase Locked Loops (PLLs). The proposed platform uses VppSim interface to compute the PLL parameters, Simplorer 7.0 environment to simulate the PLL with a VHDL-AMS description, a first optimization interface based on a genetic algorithm and a second optimization interface based on experimental designs. With the proposed platform, we have successfully adjusted the different parameters of a GPSK modulator composed of a Fractional-N Phase Locked Loop and a Sigma Delta modulator to respect the UMTS standard in terms of locking time, spurious level and phase noise.

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