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Authors
Affiliations
1 Department of ECE, Karpagam University, Coimbatore-21, IN
2 Department of ECE, Karpagam Institute Of
Engineering, Coimbatore – 21, IN
Source
Digital Signal Processing, Vol 5, No 2 (2013), Pagination: 63-66
Abstract
This paper presents design and implementation of power gating technique for combinatorial and sequential logic circuits. The trend for power reduction has been widely stated these days, the need is compensated in every way among them the best stated is the power gated technique which is best suitable in NBTI tolerant gates. The combinational and sequential circuits behave differently as one depends on clock and need extra attention. He clock circuits consume more power and so the effect of power gating is improved in the waiting and idle time periods. The experiment and comparison using hybrid NBTI tolerant effects are shown at the end and are executed in CADENCE analog environment VIRTUOSO. The results are tabulated for power gating in combinational circuit, the effect on sequential circuits will be discussed in future.
Keywords
Clock Gating, Idle Time, Power Gating, Power Reduction.
