Digital Signal Processing

Krishna M. Viswanath ¹, D. S. Harish Ram ²

Affiliations
1 Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Ettimadai, Coimbatore-641105, Tamil Nadu, IN
2 Department of ECE, Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Ettimadai, Coimbatore-641105, Tamil Nadu, IN

Abstract

The increase in scaling of technology feature size and increased levels of integration of FPGA based designs have resulted in high power-densities and temperatures. Increases in circuit density and clock speed in modern VLSI designs have brought their thermal issues into the spotlight. This paper focuses on analyzing the floorplan of FPGA Designs for temperature at System Level. The work incorporates synthesizing a NIOS-II soft-core based microprocessor system to run a Dhrystone benchmark application. The area of the generated microprocessor system is then heuristically estimated. With the estimated area, a Global Floorplan is extracted, whose thermal behavior is then analyzed using a Thermal Simulation Tool like HotSpot 5.0 for different heat spreader thicknesses. Analysis showed that the temperature distribution depends on the thickness of the heat spreader and the optimum range of the spreader thickness for the generated thermal-aware microprocessor system was obtained between 1mm to 1.2mm.

Keywords

FPGA, SOPC, Thermal Analysis, Thermal-Aware Floorplan, Area Estimation, Global Floorplan, Heat Spreader.

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