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Hemalatha, B.
- High Speed Parallel Butterfly Architecture for Computing Circular Convolution Based on FNT Using Modulo 2n+1 Partial Product Multiplier
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1 Department of Electronics and Communication Engineering, Sri Indu College of Engineering and Technology, IN
2 Department of Electronics and Communication Engineering, Sri Indu College of Engineering and Technology, IN
1 Department of Electronics and Communication Engineering, Sri Indu College of Engineering and Technology, IN
2 Department of Electronics and Communication Engineering, Sri Indu College of Engineering and Technology, IN