Data Mining and Knowledge Engineering

Open Access Open Access  Restricted Access Subscription Access
Open Access Open Access Open Access  Restricted Access Restricted Access Subscription Access

High Performance Partial Product Binary to Decimal (PPBD) Converter based Multiplier


Affiliations
1 Department of ECE, KPR Institute of Engineering and Technology, India
     

   Subscribe/Renew Journal


Decimal data processing applications have grown exponentially in recent years thereby increasing the need to have hardware support for decimal arithmetic. Multipliers are vital components of any processor or computing machine. Hence better multiplier architectures are bound to increase the efficiency of the system. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications. Throughput is the measure of how many multiplications can be performed in a given period of time. Two most common multiplication algorithms followed in the digital hardware are array multiplication algorithm and Booth multiplication algorithm. High Performance Partial Product Binary to Decimal (PPBD) Converter based Multiplier is one such promising solution. The designing can done using VERILOG and simulated, synthesized using Questa-sim.


User
Subscription Login to verify subscription
Notifications
Font Size

  • G. Jaberipur, A. Kaivani, Binary-coded decimal digit multipliers, IET Comput. Digit. Tech. (Vol: 1, Issue: 4), (2007).

  • S. Gorgin, G. Jaberipur, R. Hashemi Asl, Efficient ASIC and FPGA implementation of binary-coded decimal digit multipliers, Circuits, Syst., Signal Process. (Vol: 33, Issue: 12), (2014).

  • L. Dadda, Multi-operand parallel decimal adder: a mixed binary and BCD approach, IEEE Trans. Comput. (Vol: 56, Issue: 10), (2007).

  • J.-D. Nicoud, Iterative arrays for Radix conversion, IEEE Trans. Comput. (Vol: 20, Issue: 12), (1971).

  • L. Dadda, Some schemes for parallel multipliers, Alta Freq. (Vol: 34, Issue: 5), (1965).

  • M.S. Schmookler, A. Weinberger, High speed decimal addition, IEEE Trans. Comput. (Vol: 20, Issue: 8), (1971).


Abstract Views: 206

PDF Views: 0




  • High Performance Partial Product Binary to Decimal (PPBD) Converter based Multiplier

Abstract Views: 206  |  PDF Views: 0

Authors

R. Aswatha
Department of ECE, KPR Institute of Engineering and Technology, India
B. R. Sriram Prasath
Department of ECE, KPR Institute of Engineering and Technology, India
M. Sai Thulasi Ram
Department of ECE, KPR Institute of Engineering and Technology, India

Abstract


Decimal data processing applications have grown exponentially in recent years thereby increasing the need to have hardware support for decimal arithmetic. Multipliers are vital components of any processor or computing machine. Hence better multiplier architectures are bound to increase the efficiency of the system. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications. Throughput is the measure of how many multiplications can be performed in a given period of time. Two most common multiplication algorithms followed in the digital hardware are array multiplication algorithm and Booth multiplication algorithm. High Performance Partial Product Binary to Decimal (PPBD) Converter based Multiplier is one such promising solution. The designing can done using VERILOG and simulated, synthesized using Questa-sim.


References