Automation and Autonomous Systems

S. Ranjith ¹, N. Mathan ¹, D. Irudaya Praveen ¹, T. Ravi ¹

Affiliations
1 Sathyabama University, Chennai, Tamilnadu, IN

Abstract

This paper proposes a new topology to low power approaches for very large scale integration (VLSI) design. Power dissipation is one of the major concerns when designing a VLSI system. Until recently, dynamic power was the only concern. However, as the technology feature size shrinks, static power, which was negligible before, becomes an issue as important as dynamic power. Since static power increases dramatically in nanoscale silicon VLSI technology, the importance of reducing leakage. This paper describes a low-leakage technique. We are doing comparable analysis of different low power, leakage current reduction techniques like SLEEP approach, STACK, SLEEPY–STACK, SLEEPY KEEPER, SLEEPY–STACK with KEEPER, LEAKAGE FEEDBACK and LEAKAGE FEEDBACK with STACK techniques. Which reduces leakage power while saving exact logic state. Based on simulation results a conventional D Flip flop with the Full sleep approach achieves up to 95 % less power consumption.

Keywords

Conventional D Flip Flop, Low Power Dissipation Techniques, Circuit Simulation.

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Sree Harsha Parimi ¹, S. Mukilan ¹, T. Ravi ¹

Affiliations
1 Sathyabama University, Chennai, Tamilnadu, IN

Abstract

This paper enumerates the efficient design and analysis of a Carry Skip Adder using Full Adder cell. The Full Adder is designed using Stanford University CNTFET model and proposed 10nm CNTFET model. There are many issues facing while integrating more number of transistors like short channel effect, power dissipation, scaling of the transistors. To overcome these problems by considering the carbon nano tube have promising application in the field of electronics. The carbon nanotube is emerging as a viable replacement to the MOSFET. The transient and power analyses are obtained with operating voltage at 0.9V. The simulation results are presented and the analyses are compared with circuits designed using 32nm MOSFET. The comparison of results indicated that the proposed 10nm CNTFET based design is more efficient in power savings and speed.

Keywords

CNT, CNTFET, Full Adder Cell, Carry Skip Adder, Design Constraints and Circuit Simulation.

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Vinith Zacharia Joshy ¹, T. Ravi ¹, V. Vijayakumar ¹

Affiliations
1 Sathyabama University, Chennai, Tamilnadu, IN

Abstract

This paper enumerates the design and analysis of a Carry Select Adder (CSA) using Full Adder cell. The Full Adder is designed using MOSFET 32nm model, Stanford University CNTFET model and proposed 10nm CNTFET model. There are many issues facing while integrating more number of transistors like short channel effect, power dissipation, scaling of the transistors. Inorder to overcome these problems and still reduce transistor size, Carbon Nano Tube Field Effect Transistors or CNTFETs have promising applications in the field of electronics. The carbon nanotube is emerging as a viable replacement to the MOSFET. The transient and power analyses in this paper are obtained with operating voltage at 0.9V. The simulation results are presented and the analyses are compared with circuits designed using 32nm MOSFET. The comparison of results indicated that the proposed 10nm CNTFET based design is more efficient in power savings and speed.

Keywords

CNT, CNTFET, Full Adder Cell, Carry Select Adder, Design Constraints, Circuit Simulation, CSA, 32nm, 10nm, Ballistic CNTFET Model, HSPICE, TSPICE.

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