Mody University International Journal of Computing and Engineering Research

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Design of Two Stage CMOS Comparator with Improved Accuracy in Terms of Different Parameters


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1 ECE Department, School of Electrical Sciences, K L University, Vijayawada, Andhra Pradesh, India
 

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The well developing industry of electronics is insistent to low power and high speed and less area ADCs (analog to digital converters). Comparator is device that is especially employed in ADCs, used for division method, associated for square measure and chiefly liable for delay created and power consumption by an ADC. A low power and high speed comparator is needed to satisfy the longer term demands. The circuit conferred during this paper is designed using 0.35μm CMOS technology with 1.65V bias voltage and 12μA bias current. Cadence virtuoso tool is employed for the designing and simulation for the comparator circuit. The correct analysis of propagation delay, settling time, speed of the comparator is mentioned very well in detail.

Keywords

CMOS Technology, Propagation Delay, Settling Time, Speed.
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  • P. Allen, and D. Holmberg, CMOS Analog Circuit Design, 2nd ed., 1998.

  • S. Suman, “Design of efficient ring VCO using nano scale double gate MOSFET,” Mody University International Journal of Computing and Engineering Research, vol. 2, no. 1, pp. 05-10, 2018.

  • S. Suman, K. G. Sharma, and P. K. Ghosh, “250 MHz multiphase delay locked loop for low power applications,” International Journal of Electrical and Computer Engineering, vol. 7, no. 6, pp. 3323-3331, December 2017.

  • S. Yellampalli, and A. Srivastava, “A comparator-based I/sub DDQ testing of CMOS analog and mixed-signal integrated circuits,” in 48th Midwest Symposium on Circuits and Systems, IEEE, 2005.

  • H. Saini, and S. Suman, “Analysis of different single-stage amplifiers,” Mody University International Journal of Computing and Engineering Research, vol. 1, no. 2, pp. 100-103, 2017.

  • S. Suman, and B. P. Singh, “Design of temperature sensor using ring oscillator,” International Journal of Scientific & Engineering Research, vol. 3, no. 5, pp. 1-7, May 2012.

  • S. Suman, K. G. Sharma, and P. K. Ghosh, “Design of PLL using improved performance ring VCO,” in International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT’2016), Chennai, India, pp. 3478-3483, March 2016.

  • S. Suman, K. G. Sharma, and P. K. Ghosh, Voltage Controlled Ring Oscillators: Design Prospective and Applications, LAMBERT Academic Publishing, Germany, January 2018.

  • S. Suman, K. G. Sharma, and P. K. Ghosh, “Performance analysis of voltage controlled ring oscillators,” in S. Satapathy, Y. Bhatt, A. Joshi, and D. Mishra, (eds.) Proceedings of the International Congress on Information and Communication Technology, Advances in Intelligent System and Computing, vol. 439, chapter 4, Springer, pp. 29 - 38, 2016.

  • N. Tarun, S. Suman, and P. K. Ghosh, “Design of low voltage improved performance current mirror,” Control Theory and Informatics, vol. 4, no. 2, pp. 26-38, 2014.

  • B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., Tata Mc-Graw Hill, 2001.

  • Jhon, and K. Martin, Analog Integrated Circuit Design, Wiley India Pvt. Ltd, 1997.

  • R. J. Baker, H. W. Li, and D. E. Boyce, CMOS Circuit Design, Layout and Simulation, Series on microelectronic systems, IEEE Press, 2003.

  • P. M. Furth, Y.-C. Tsen, V. B. Kulkurni, and T. K. Poriyani, “On the design of low-power CMOS comparators with programmable hysteresis,” in 53rd IEEE International Midwest Symposium on Circuits and Systems, IEEE, 2010.

  • F. Fiori, “Investigation on the susceptibility of two-stage voltage comparator to EMI,” in 8th Workshop on Electromagnetic Compatibility of Integrated Circuits, IEEE, 2011.

  • Y. Q. Chen, B. Wang, Y. F. Zhang, Y. F. En, Y. Huang, Y. D. Lu, L. X. Liu, and X. H. Wang, “Design of prognostic circuit for electromigration failure of integrated circuit,” in Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), IEEE, 2013.


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  • Design of Two Stage CMOS Comparator with Improved Accuracy in Terms of Different Parameters

Abstract Views: 193  |  PDF Views: 211

Authors

Shruti Suman
ECE Department, School of Electrical Sciences, K L University, Vijayawada, Andhra Pradesh, India

Abstract


The well developing industry of electronics is insistent to low power and high speed and less area ADCs (analog to digital converters). Comparator is device that is especially employed in ADCs, used for division method, associated for square measure and chiefly liable for delay created and power consumption by an ADC. A low power and high speed comparator is needed to satisfy the longer term demands. The circuit conferred during this paper is designed using 0.35μm CMOS technology with 1.65V bias voltage and 12μA bias current. Cadence virtuoso tool is employed for the designing and simulation for the comparator circuit. The correct analysis of propagation delay, settling time, speed of the comparator is mentioned very well in detail.

Keywords


CMOS Technology, Propagation Delay, Settling Time, Speed.

References