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Dutta, Umesh
- Noise Tolerance Enhancement with Leakage Current Reduction in Dynamic Logic Circiuts
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1 Manav Rachna International University, Faridabad-121004, Haryana, IN
1 Manav Rachna International University, Faridabad-121004, Haryana, IN
Source
International Journal of Scientific Engineering and Technology, Vol 1, No 3 (2012), Pagination: 137-141Abstract
To improve noise tolerance of the dynamic logic circuits with leakage current reduction , a new noise tolerant technique is proposed here. Average noise threshold energy (ANTE) metric is used to compare the noise tolerance ability of the existing techniques with the proposed technique. A two input AND gate is designed and simulated using 0.18 micron technology and at a clock frequency of 100MHz. Simulation results indicate that the proposed technique provides an improvement of 77.72% in ANTE with a reduction of leakage current by 73.9% over the conventional domino technique.Keywords
ANTE, Noise Tolerance, Dynamic Circuits, Crosstalk, Power Consumption.- Design of Low Voltage and Low Power D-Flip Flop
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Authors
Affiliations
1 Manav Rachna International University, Sector-43, Faridabad-121004, Haryana, IN
1 Manav Rachna International University, Sector-43, Faridabad-121004, Haryana, IN