Informatics Publishing Limited

Umesh Dutta ¹, Pankaj Kumar ¹, Naresh Kumar ¹

Affiliations
1 Manav Rachna International University, Faridabad-121004, Haryana, IN

Abstract

To improve noise tolerance of the dynamic logic circuits with leakage current reduction , a new noise tolerant technique is proposed here. Average noise threshold energy (ANTE) metric is used to compare the noise tolerance ability of the existing techniques with the proposed technique. A two input AND gate is designed and simulated using 0.18 micron technology and at a clock frequency of 100MHz. Simulation results indicate that the proposed technique provides an improvement of 77.72% in ANTE with a reduction of leakage current by 73.9% over the conventional domino technique.

Keywords

ANTE, Noise Tolerance, Dynamic Circuits, Crosstalk, Power Consumption.

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Naresh Kumar ¹, Umesh Dutta ¹, Dileep Kumar ¹

Affiliations
1 Manav Rachna International University, Sector-43, Faridabad-121004, Haryana, IN

Abstract

This paper presents a novel D flip-flop for low voltage operation with improved speed using SPICE simulation, it takes advantage of a dynamic threshold voltage using DTMOS for ultra-low voltage operation and a negative differential resistance storage using Bistable Gated Bipolar Device (BGB). DTMOS provides low power consumption and BGB provides high speed because of less capacitance. So we have taken advantages of both the DTMOS and BGB device to make the D-Flip Flop for low power operation with high speed and low leakage current. Leakage is further reduced by addition of two sleep transistors.

Keywords

BGB, DTMOS, CMOS and sleep Transistor.

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