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Ahmed, Shakil
- An Effective Storage Encryption Solution
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Authors
Affiliations
1 Computer and Communication Systems Department, Faculty of Engineering, University Putra Malaysia, 43400 Serdang
1 Computer and Communication Systems Department, Faculty of Engineering, University Putra Malaysia, 43400 Serdang
Source
Indian Journal of Science and Technology, Vol 6, No 4 (2013), Pagination: 4384-4389Abstract
It is always being a concern since many years that data moving in networks must be secured from eavesdropping. Data encryption is considered one of the effective methods which challenge cryptanalyst to find the useful information from the encrypted data. Recently this focus has now shifted to encrypting data at rest that is encrypting data for secondary storage devices. The usefulness of this data encryption method is always a challenge for cryptographic researchers to prevent it from cryptanalyst attacks. AES-XTS is the method of encrypting data that is designed for storage devices that provides encryption based on tweak value which makes it less vulnerable for cryptanalyst attacks. This mode has been recently implemented on software as well as hardware. The FPGA provides a way to achieve the fast encryption process with sustainable throughput with a little cost. This paper presents an implementation of AES-XTS on FPGA using memory based pipelined design. After successful synthesizing, placement and routing we got the highest efficiency of the proposed design. The implementation is being incorporated by using the Digital Clock Manager (DCM) feature of FPGA with two DCMs are cascaded with the incorporation of on-the-fly key generation to achieve the time effective implementation and also an enhanced implementation of one of the AES sub-modules is incorporated. The proposed scheme is implemented on Virtex V- XC5vlx50-3ff676 FPGA.Keywords
Cryptography, XTS-AES, FPGA, PipeliningReferences
- Mancillas-López C, Chakraborty D et al. (2010). Reconfigurable hardware implementations of tweakable enciphering schemes, IEEE Transactions on Computers, vol 59(11), 1547-1561.
- Liskov M, Rivest R L et al. (2011). Tweakable block ciphers, Journal of cryptology, vol 24(3), 588-613.
- El-Fotouh, and Diepold (2008). A New Narrow Block Mode of Operations for Disk Encryption, Fourth International Conference on Information Assurance and Security, ISIAS’08, 126-131.
- Hars L (2007). Discryption: Internal hard-disk encryption for secure storage, Computer, vol 40(6), 103-105.
- Laird C (2007). Taking a hard-line approach to encryption, Computer, vol 40(3), 13-15.
- Kallath D (2005). Trust in trusted computing-the end of security as we know it, Computer Fraud & Security, vol 2005(12), 4-7.
- Zambreno J, Nguyen D et al. (2004). Exploring area/delay tradeoffs in an AES FPGA implementation, Field Programmable Logic and Application, vol 3203, 575-585.
- Subashri T, Arunachalam R et al. (2010). Pipelining Architecture of AES Encryption and Key Generation with Search Based Memory, Recent Trends in Network Security and Applications, vol 89, 224-231.
- Gaj K, and Chodowiec P (2009). FPGA and ASIC implementations of AES, Cryptographic Engineering, 235-294.
- Xilinx I (2009). Digital Clock Manager (DCM) module. 1-6. Available from http://www.xilinx.com/support/documentation/ip_documentation/dcm_module.pdf
- Drimer S, Güneysu T et al. (2010). DSPs, BRAMs, and a pinch of logic: Extended recipes for AES on FPGAs, ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol 3(1).
- Ahmed S, Samsudin K et al. (2011). Effective implementation of AES-XTS on FPGA, TENCON 2011-2011 IEEE Region 10 Conference, 184-186.
- Bulens P, Standaert F X et al. (2008). Implementation of the AES-128 on Virtex-5 FPGAs, Progress in Cryptology-AFRICACRYPT 2008, 16-26.
- Rahman T, Pan S et al. (2010). Design of a High Throughput 128-bit AES (Rijndael Block Cipher), Proceedings of the International MultiConference of Engineers and Computer Scientists.
- Algredo-Badillo I, Feregrino-Uribe C et al. (2010). Efficient hardware architecture for the AES-CCM protocol of the IEEE 802.11 i standard, Computers & Electrical Engineering, vol 36(3), 565-577.
- Saggese G, Mazzeo A et al. (2003). An FPGA-based performance analysis of the unrolling, tiling, and pipelining of the AES algorithm, Field Programmable Logic and Application, vol 2778, 292-302.
- Zhang Q (2010), On a Hardware Implementing Method of the Optimized AES Encryption Algorithm, 2010 Second International Conference on Multimedia and Information Technology (MMIT), vol 1, 82-84.
- Nedjah N, Mourelle L M et al. (2006). A compact piplined hardware implementation of the aes-128 cipher, Third International Conference on Information Technology: New Generations, ITNG 2006, 216-221.
- Chodowiec P and Gaj K (2003). Very compact FPGA implementation of the AES algorithm, Cryptographic Hardware and Embedded Systems-CHES 2003, vol 2779, 319-333.
- Rais M H, and Qasim S M (2009). Efficient hardware realization of advanced encryption standard algorithm using Virtex-5 FPGA, International Journal of Computer Science and Network Security, vol 9(9), 59-63.
- Granado-Criado J M, Vega-Rodríguez M A et al. (2010). A new methodology to implement the AES algorithm using partial and dynamic reconfiguration, Integration, the VLSI Journal, vol 43(1), 72-80.
- Helion ed. (2008). Fast AES XTS/CBC Core for Xilinx FPGA.
- Hatzidimitriou E, and Kakarountas A P (2010). Implementation of a P1619 crypto-core for Shared Storage Media, MELECON 2010-2010 15th IEEE Mediterranean Electrotechnical Conference, 597-601.
- Discretix ed.(2009). Secure Disk Solution (DxSD).
- Dworkin M (2010). Recommendation for Block Cipher Modes of Operation: The XTS-AES Mode for Confidentiality on Storage Devices, NIST Special Publication.
- I. S. i. S. W. Group ed., IEEE P1619/D19: Draft standard for cryptographic protection of data on block-oriented storage devices.
- Elliptic ed. (2009). XTS-AES Core
- Multiphase Flow Control with Embedded System and Color Image Processing
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Authors
Affiliations
1 Department of Computer Engineering, Sir Syed University of Engineering and Technology, Karachi, PK
1 Department of Computer Engineering, Sir Syed University of Engineering and Technology, Karachi, PK