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Deepika, M.
- Design of Low Power Layered Decoding Architecture for Low Density Parity Check Decoder
Authors
1 K. S. Rangasamy College of Technology, Namakkal Dist. Tamilnadu, IN
Source
Wireless Communication, Vol 4, No 1 (2012), Pagination: 44-48Abstract
Low Density Parity Check (LDPC) Decoder is an iterative decoding process. It requires large amount of memory access which leads to high power consumption. Layered decoding provides efficient and high throughput implementation of LDPC decoders. The row based or column based layered scheduling is introduced to reduce the iteration number. Memory bypassing scheme is proposed to achieve optimal reduction of memory access and to minimize power. Layered decoding approach is explored to reduce the critical path of the layered LDPC decoder. LDPC codes not only exhibit very good error-correcting performance but also effectively fit to partially parallel VLSI decoder implementations.Keywords
VLSI, LDPC (Low Density Parity Check), Parity Check Matrix, Low Power.
- Simulation of Algan Channel High Electron Mobility Transistor Using Sentaurus TCAD
Authors
1 Department of Information and Communication Engineering, S.K.P Engineering College, Thiruvannamalai-606611, IN
Source
Digital Signal Processing, Vol 7, No 3 (2015), Pagination: 89-91Abstract
Enhanced performance of RF power modules is required in a information society. To satisfy these requirements, so designed a novel High-Electron Mobility Transistor (HEMT) structure employing wider bandgap AlGaN for a channel layer, which we called AlGaN channel HEMT. The wider bandgap is more effective for higher voltage operation of HEMTs and contributes to the increase of output power in RF power modules. As a result, fabricated Al-GaN channel HEMTs had much higher breakdown voltages than those of conventional GaN channel HEMTs with good pinchoff operation and sufficiently high drain current density without current collapse. Furthermore, specific ON-state resistances of fabricated AlGaN channel HEMTs were competitive with the best values of reported GaN- and SiC-based devices with similar breakdown voltages.- Wave Pipelined Structure for Pipelined FFT Architecture
Authors
1 School of Computing, SASTRA University, Thanjavur - 613401, Tamil Nadu, IN
Source
Indian Journal of Science and Technology, Vol 9, No 29 (2016), Pagination:Abstract
Wave Pipelining has been used in order to reduce the area without degrading its performance and also to improve the speed. In pipelining the throughput is achieved with the compensation of area and the critical path will be same as the original architecture. While considering of larger circuits the area places an important role where the cost is a major issue. Hence in order to reduce the area the latches are removed which produces the technique of wave pipelining. The concept of Wave Pipelining optimize the area and speed when compared to the pipelining architectures. Thus the Wave Pipelining is applied in the FFT architecture for achieving less area. The FFT pipelined architecture is based on splitting the architecture by stages. Each stage is evaluated with effective structure. It’s noted that by using the internal clock which increases both speed and reduces clock loads the number of gates used in the pipelined structure is reduced in using wave pipelining. The Wave Pipelining technique have to be implemented in a 32-bit FFT Pipelined architecture which is suitable for a digital signal processing applications for image processing and for conversion of frequency domain to time domain. And to compare the area and speed of the WP architecture and pipelined architecture.Keywords
DIF, DIT, Multiplier, Pipelining, 32-bit FFT Processor, Wave Pipelining (WP).Full Text
- Energy Audit in College Campus
Authors
1 Department of Electrical and Electronics and Engineering, KPR Institute of Engineering and Technology
2 Department of Electrical and Electronics and Engineering, KPR Institute of Engineering and Technology, IN
Source
Software Engineering, Vol 11, No 2 (2019), Pagination: 32-33Abstract
Energy demand is an existing problem for the developing country like India. The energy generation plays a vital role in the economic growth of the country. India is the third largest power generator and the third largest power consumer in the world, energy demand and scarcity rules the country. Energy audit and conservation can be the best solution for the raising energy demand. This project describes the energy audit methodology for the organization. Nowadays in the new trends of power market, it is a very difficult task to satisfy the power balance concepts even though the consumers are able to pay their costly demands. So the energy conservation and energy management concepts are necessary for the flexible utilities. The energy audit is a process to identify the facilities from different areas. An energy auditing system inspects and analyses the flow of energy to cut back energy consumption while not affecting the number and quality of productions undesirably. Energy monitoring is one of the important applications arising from research in Internet of Things. Suggesting the methods which reduce the energy consumption and cost of utilization. Methods such as type of lamps and fans can be used to reduce the consumption of energy. Also provides Energy monitoring system for classroom using Internet of Things. The system provides the periodic energy consumption data of the loads in the class room.
Keywords
IoT-Internet of Things, LCD-Liquid Crystal Display, Wi-Fi -Wireless Fidelity.References
- Neil Stephen Lopez , Jeremias Gonzaga , Laurence A. Gan Lim, “Energy Audit and Analysis of Electricity Consumption of an Educational Building Philippines for smart consumption,” 2017 IEEE 9th International Conference on Humanoid, Nanotechnology, Information Technology, Communication and Control, Environment and Management (HNICEM)
- Chikku Abraham, Mel George, Victor Jose, Sharath Deshpande, “Energy Audit of IIT-Bombay Campus”, July 2008.
- Nissanga Nishad, Rasanajan Mendis, Nisal Perer, “Energy Audit: A Case Study” ‖International Conference on Information and Automation, 2006.
- D. C. Maheepala, R. M. N. Nayanajith, M. W. R. P. Somarathna, R. A. A. M. Bandara, K. T. M. U. Hemapala, “Designing an Energy Monitoring, Analysing and Solution Providing System for Energy Auditing,” 2018 Fourth International Conference on Advances in Electrical, Electronics, Information, Communication and Bio-Informatics (AEEICB)
- C. C. Aggarwal, N. Ashish and A. Sheth, "The Internet of Things: A Survey from the Data-Centric Perspective," in Managing and Mining Sensor Data, Springer US, 2013.