Informatics Publishing Limited

S. Dhamodharan ¹, R. Balakumaresan ², K. Vadivel ³

Affiliations
1 Department of Electronics and Communication, SSM Institute of Engineering and Technology, Dindigul, Tamilnadu, IN
2 Department of Electronics and Communication, RVS School of Engineering and Technology, Dindigul, Tamilnadu, IN
3 Department of Mechanical Engineering, SSM Institute of Engineering and Technology, Dindigul, Tamilnadu, IN

Abstract

With the relentless shrinking of the minimum feature size of VLSI Integrated Circuits (ICs) and due to the radiation strike on VLSI chips, the charge is dumped on the diffusion node. This creates a large voltage spike. With operating voltages getting smaller, this problem is further aggravated. As a result, modern VLSI ICs are significantly more prone to Single Event Transient (SET) problems. So a Single Event Transient Suppressor for Flip Flops is designed which reduces glitches. A SET suppressor circuit was designed which mitigated SETs by adjusting the clock edge timing. However the architecture consumes high power proportionate to the circuit. So a Single Event Transient Suppressor along with Multi Vth level convertor for Flip Flops is proposed. Here, the lowering of supply voltage by means of employing multiple voltage supply reduces the power consumption in the circuit. The proposed design is implemented in MICROWIND 3.5 and simulated using DSCH. Simulation analysis shows that the SET Suppressor along with Multi Vth level convertor reduces the power consumption by 15% and delay by 34% compared with SET Suppressor for Flip Flops. The Flip-Flops using the SET suppressors along with the Multi Vth level convertors are typically useful in mixed asynchronous and synchronous circuits for low power applications.

Keywords

Single Event Upset, Single Event Transient, Multi Vth Level Convertors.

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