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Senthilkumar, J.
- Effect of Polychlorinated Biphenyl (Aroclor 1254) on Rat Leydig Cellular Antioxidant System
Abstract Views :184 |
PDF Views:0
Authors
P. Murugesan
1,
J. Senthilkumar
1,
K. Balasubramanian
1,
M. M. Aruldhas
1,
P. Govindarajulu
1,
J. Arunakaran
1
Affiliations
1 Department of Endocrinology, Dr. ALM PG Institute of Basic Medical Sciences, University of Madras, Taramani, Chennai-600 113, IN
1 Department of Endocrinology, Dr. ALM PG Institute of Basic Medical Sciences, University of Madras, Taramani, Chennai-600 113, IN
Source
Journal of Endocrinology and Reproduction, Vol 7, No 1&2 (2003), Pagination: 91-92Abstract
To find out the effect of polychlorinated biphenyl compound Aroclor 1254 on rat Leydig cellular antioxiSant system, adult male rats were exposed to Aroclor 1254 (2 mg/kg b.wt.) mixed with com oil through intraperitoneal (ip) injection daily for 30 days. The control rats were administered com oil as vehicle. Testes were removed on the both groups and Leydig cells were isolated by enzymatic digestion and purified on discontinous percoll gradient.
- Pipelined FIR Filter Implementation Using FPGA
Abstract Views :153 |
PDF Views:0
To enhance system speed and reducing implementation complexity, a lot of work has been done in the process of achieving digital signal processing by use of the FPGA. In a filter the pipelining of multiplication is achieved by shifts and addition method. This paper describes the design of Third order low pass FIR filter with pipelined architecture. The design synthesis is done using Xilinx ISE 12.1 and implemented in Spartan-3E FPGA. By pipelining the delay of FIR filters can be reduced. Pipelined technique may reduce delay and enhances speed as compared to non-pipelined technique.
Authors
Affiliations
1 Department of Electronics and Communication Engineering, Mepco Schlenk Engineering College, Sivakasi, IN
1 Department of Electronics and Communication Engineering, Mepco Schlenk Engineering College, Sivakasi, IN
Source
International Journal of Scientific Engineering and Technology, Vol 1, No 4 (2012), Pagination: 55-60Abstract
FIR filters are being designed using HDL languages to enhance the speed of the system. In the whole system if the speed of the individual block is enhanced, the overall speed of the system is enhanced. In order to attain effective utilization hardware is done by applying the pipelining technique. Pipelining is an implementation technique in which multiple instructions are overlapped in execution. The proposed design of this paper is an attempt to optimize the system speed with minimal cost and hardware. The central design concept is to build filters with higher operating frequency without sacrificing the performance of original filters.To enhance system speed and reducing implementation complexity, a lot of work has been done in the process of achieving digital signal processing by use of the FPGA. In a filter the pipelining of multiplication is achieved by shifts and addition method. This paper describes the design of Third order low pass FIR filter with pipelined architecture. The design synthesis is done using Xilinx ISE 12.1 and implemented in Spartan-3E FPGA. By pipelining the delay of FIR filters can be reduced. Pipelined technique may reduce delay and enhances speed as compared to non-pipelined technique.
Keywords
FIR Filter, Non Pipelining, Pipelining, FPGA.Full Text
- Real Time Two Hop Neighbour Strategic Secure Routing with Attribute Specific Blockchain Encryption Scheme for Improved Security in Wireless Sensor Networks
Abstract Views :264 |
PDF Views:2
Authors
Affiliations
1 Department of Biomedical Engineering, Mahendra Institute of Technology, Namakkal, Tamil Nadu, IN
2 Department of Information Technology, Sona College of Technology, Salem, Tamil Nadu, IN
3 Department of Electronics and Communication Engineering, Sona College of Technology, Salem, Tamil Nadu, IN
1 Department of Biomedical Engineering, Mahendra Institute of Technology, Namakkal, Tamil Nadu, IN
2 Department of Information Technology, Sona College of Technology, Salem, Tamil Nadu, IN
3 Department of Electronics and Communication Engineering, Sona College of Technology, Salem, Tamil Nadu, IN
Source
International Journal of Computer Networks and Applications, Vol 8, No 4 (2021), Pagination: 300-310Abstract
Wireless Sensor Network (WSN) is most vulnerable to routing attacks which affects the confidentiality and integrity services of the data transmitted between any nodes. Many research efforts have been taken to propose secure routing schemes for improving the data security against routing attacks in WSN. The existing secure routing schemes are not able to dynamically discover the trust path between nodes for ensuring secure transmission without compromising confidentiality and integrity service. To address this issue, a real-time, two-hop neighbour, strategically secure routing scheme is proposed in this paper. According to the strategy of two-hop neighbours, the method selects the forwarding node according to the trust measures computed based on trust energy support and trust forwarding support of the two hop nodes. Further, the data security is enforced at the attribute level. The Blockchain mechanism is enforced where a single block contains information of specific attribute of data which restrict the user who have access to the attribute only can read the data present in the block. The data encryption is performed according to different encryption standards maintained by the system, unique for different attributes. According to the Hash code present in the Blockchain, the user can decode the key and scheme to obtain the original data. The proposed approach improves the performance in secure routing and increases the data security performance.Keywords
WSN, Data Security, Secure Routing, Two Hop Neighbour Strategy, Blockchain, QoS.Full Text
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