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Jaya, J.
- Detection of Suspicious Region in Medical Images Using Metaheuristic Algorithms
Abstract Views :179 |
PDF Views:4
Authors
J. Jaya
1,
K. Thanushkodi
2
Affiliations
1 Anna University, IN
2 ACET, Coimbatore, IN
1 Anna University, IN
2 ACET, Coimbatore, IN
Source
Artificial Intelligent Systems and Machine Learning, Vol 2, No 9 (2010), Pagination: 219-222Abstract
The overall motivation of this paper is the implementation of detection of suspicious region from the medical images using metaheuristic algorithms. Segmentation is the very essential stage for extracting the region of interest (ROI) fr4om the medical images. In this paper Genetic algorithm and parallel Ant colony optimization techniques are used for the detection of MRI brain tumor.Keywords
MRI, Genetic Algorithm, Parallel Ant Colony Optimization (PACO).
- VLSI Usage of a Productive MBIST Architecture Utilizing RLFSR
Abstract Views :149 |
PDF Views:0
Authors
Affiliations
1 Department of Electronics and Communication Engineering, Nehru Institute of Engineering and Technology, IN
2 Department of Electronics and Communication Engineering, Hindusthan College of Engineering and Technology, IN
1 Department of Electronics and Communication Engineering, Nehru Institute of Engineering and Technology, IN
2 Department of Electronics and Communication Engineering, Hindusthan College of Engineering and Technology, IN
Source
ICTACT Journal on Microelectronics, Vol 7, No 2 (2021), Pagination: 1134-1140Abstract
This article introduces a power efficient application of FPGA created through a Memory Built in Self Test (MBIST). It has 2-bit Linear Feedback Shift Register (LFSR) array, which changes the direction of the previous process and creates high MBIST structures. This unwanted change affects all MBIST’s power consumption. The proposed MBIST with LFSR ring reduces the power consumption problem. The 2-bit 2N bit model generator is connected to the 2-bit (N-2) and 2-bit 4-bit (N-2) LFSR model generator, which are separately controlled using two separate clocks with two different frequencies, creating each location address high memory test. The proposed architecture has been implemented on Vertex4 FPGA technology in Xilinx software. The results enhance proposed design’s performance when compared it with the existing design.Keywords
Xilinx, FPGA, Switching Activity, 2D-LFSR, Ring LFSR (RLFSR), Memory Built in Self Test (MBIST).References
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