Informatics Publishing Limited

K. Hari Kishore ¹, Fazal Noorbasha ², Habibulla Khan ³, Asiya Begum ¹, Y. Rajasekhar Reddy , K. Anil Kumar

Affiliations
1 Department of ECE, KL University, Vijayawada, A.P, IN
2 Department of Electronics and Communication Engineering, KL University, Guntur, Andhra Pradesh, IN
3 Department of Electronics & Communication Engineering, KL University, Vijayawada, AP, IN

Abstract

Any VLSI circuit is composed of the very basic unit that is the multiplier. As technology is increasing day by day many new designs are being evolved. As the design becomes bigger more will be the delay in it. If the delay in the basic unit that is multiplier can be decreased then the overall delay in the new designs can be effectively alleviated. There are many multipliers designed so far in the field of VLSI using different methods for its implementation. This paper presents implementation of a Modified Booth multiplier. So far many Modified Booth multipliers are implemented. In all the methods for generating the partial products 'negi' the extra partial product bit is used due to which number of partial products generated will be N/2+1. If this 'negi' bit in the partial products can be avoided and efficient way for generating 2's complement of negative partial product is used which generates conversion signals, and then the number of partial products will decrease to N/2. For addition of partial products the design uses the 4:2 compressors to reduce the complexity in the circuit involved.

Keywords

Modified Booth Multiplier, Partial Product, Conversion Signal, 4:2 Compressors.

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T. Sridevi ¹, Habibulla Khan ¹, Ch. Sindhu ¹, P. Naga Praveen Kumar ², P. Sagar ¹

Affiliations
1 Department of ECE, KL University, Vijayawada, A.P, IN
2 Department of ECE, KL University, Vijayawada, A.P, IN

Abstract

Number Plate Recognition systems are used to track and monitor the moving vehicles by automatically extracting the number plates. The objective of this system is to recognize vehicles based on license plate information. Number plate recognition is part of vehicle identification system. Now a days it has wide range of applications like traffic surveillance, access control etc. The images of passing vehicles are taken at surveillance system and those images will be processed. The Proposed method uses simple morphological open and close operations using different structuring elements for plate feature extraction, Labeling the connected pixels, searching the plate location based on Geometrical conditions, segmenting the number plate and character recognition with Neural Network of Multilayer Perceptron. We have proposed a new method for plate segmentation based on Labeling. This method has been tested using a database of Indian number plates and results achieved have shown the high detection rate than existing methods.

Keywords

Morphological Operations, Labeling, Plate Segmentation, Multi Layer Perceptron.

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B. Murali Krishna ¹, G. L. Madhumati ², Habibulla Khan ¹

Affiliations
1 Department of ECE, K L University, AP, IN
2 Department of ECE, Dhanekula Institute of Engineering and Technology, AP, IN

Abstract

Background: Field Programmable Gate Arrays (FPGAs) are unlimited by applications, but fortunately limited with area. FPGAs can be integrated to various fields like system-on-chip, communication, cryptography, signal and image processing etc. Methods: The main purpose of this research paper is to implement multiple applications on FPGA by interfacing with various peripherals like Universal Asynchronous Receiver Transmitter (UART), General-Purpose Input/Output (GPIO) and Digital Video Interface (DVI) - Video Graphics Array (VGA) using Partial Reconfiguration (PR). Findings: The UART peripheral is used for dual purposes. First purpose is to switch the applications dynamically using PR, and second purpose serves a, design of N-bit adder and subtractor applications in serial communication, GPIO's are used to design various Linear Feedback Shift Register (LFSR) techniques which are applicable in cryptography system which generates random keys encrypted with message produces cipher can encrypt and decrypt data in wireless with ZigBee peripheral devices, and LFSR is used in Built-In-Self-Test to generate test patterns for a digital system under test. Digital Video Interface peripheral is used to design ZigBee based wireless video game. A comparative analysis is performed among spartan, virtex5 and virtex6 architectures. It has been observed that virtex6 architecture consumes fewer resources in comparison to Spartan and virtex5. Moreover, a wireless remote control is designed using ZigBee to provide the gaming control to the user. Conclusion: Applications implemented using various peripherals can be switched dynamically with loading partially configured bit streams in CF card to FPGA by providing commands in serial communication through MicroBlaze Processor.

Keywords

DVI, FPGA, GPIO’s and ZigBee, Partial Reconfiguration, UART.

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Srinivasa R. Vempati ¹, Habibulla Khan ², Anil K. Tipparti ³

Affiliations
1 Department of ECE, Anurag Engineering College, Kodad - 508206, Telangana, IN
2 Department of ECE, KL University, Vaddeswaram - 522502, Andhra Pradesh, IN
3 Department of ECE, SVS Group of Institutions, Hanamkonda - 506001, Telangana, IN

Abstract

Background: Combined effect of fading and shadowing degrades the performance of multiple access wireless communication systems. The presence of impulsive type non-Gaussian noise along with inters symbol interference and multiple access interference further worsens the system performance. Methods: This paper presents a multiuser detection technique for direct sequence-code division multiple accesses systems over generalized-K fading channels in presence of impulsive noise modeled by Laplace distribution. Maximal ratio combining receive diversity technique is also incorporated to mitigate the effects of simultaneous presence of fading and shadowing. An M-decorrelator is proposed to robustly detect the binary phase shift keyed symbols. Performance of proposed M-decorrelator is evaluated by computing the average probability of error. Findings: The proposed M-decorrelator performs better in the simultaneous presence of fading, shadowing and impulsive noise when compared to least squares, Huber and Hampel M-estimator based detectors.

Keywords

Impulsive Noise, Laplace Noise, M-Estimator, Multiuser Detection, Probability of Error.

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Harikishore Kakarla ¹, M. Madhavi Latha ², Habibulla Khan ¹

Affiliations
1 Dept. of ECE, KL University, Vijayawada, AP, IN
2 Dept. of ECE, JNTUH, Hyderabad, AP, IN

Abstract

As with the increase in data density the probability of error happening in data transfer has increased the need for error free coding technique is in greater demand. In this paper an optimal approach for the processing of self correcting logic in faulty condition during coding and decoding operation is developed. The process of digital designing and its evaluation for realization is presented. The implementation of proposed design on Xilinx-FPGA device is presented.

Keywords

Error Free Coding, Memory Operation, Self Correcting Logic, Forward Error Correction.

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