Informatics Publishing Limited

D. Jackuline Moni ¹, H. Victor Du John ¹

Affiliations
1 Department of Electronics and Communication Engineering, Dept, Karunya University, Coimbatore, IN

Abstract

The necessity of wireless ECG transmission is increasing in day to day life. To transmit the ECG signal, the conversion of analog ECG to digital is more important and the same is achieved using analog to digital converters. This paper concentrates on the design of charge redistribution successive approximation type ADC in 180nm CMOS technology. This analog to digital converter is designed for the use of wireless medical ECG applications with the sampling rate of 5KS/s and 10 bit resolution for the input range of 10mv, since the ECG signal having very less amplitude. The principle used in this paper is charge redistribution adiabatic charging type digital to analog converter in the ADC circuit which consumes very less power. The regenerative comparator in the ADC also reduces the power consumption of the circuit. The digital output is collected from the SAR register which is constructed using flip-flops which can act as a ring counter. The SAR register gets the input from the regenerative comparator which is the error signal of the comparator from charge redistribution DAC and S&H. The whole circuit is driven by the clock input. This ADC will be more suitable for low frequency medical applications consuming 8.3μW at 1.2V supply voltage. Noise analysis is done and jitter noise is reduced.

Keywords

Charge Redistribution, Jitter Noise, Regenerative, SAR-ADC.

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D. S. Shylu ¹, D. Jackuline Moni ²

Affiliations
1 ECE Department, Karunya University, Coimbatore-641114, IN
2 ECE Department, Karunya University, Coimbatore-641114, IS

Abstract

Among various ADC architectures, a pipelined ADC is suitable for high-speed, high-resolution, and low-power operation. The presented architecture utilizes a combination of two power reduction techniques such as split capacitor Correlated Double sampling (SC-CDS) technique and op-amp sharing technique. Using this approach a 10 bit 60MSPS pipelined ADC has been designed in a 180nm CMOS technology. Also power comparison of 10-bit Pipelined ADC with Sample-and-hold-amplifier (SHA) and without SHA is also performed. Simulation results shows a power consumption of 15.7mW with SHA and 3.19mW without SHA from a 1.8V supply voltage using CADENCE software.

Keywords

Pipelined ADC, Differential Dynamic Latch Comparator, Low Power, OP-Amp Sharing Technique.

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J. Ajayan ¹, D. Jackuline Moni ²

Affiliations
1 Anna University, Tamilnadu, IN
2 Karunya University, Tamilnadu, IN

Abstract

In this paper, the performance of Symmetric Extended Source/Drain Schottky Tunneling Transistor (ESD-ST-SOIFET) with different gate structures are investigated through a TCAD modeling study and compared with the performances of STSFET and conventional CMOS devices. The Symmetric Extended Source/Drain Schottky Tunneling Transistor has the source/drain regions replaced with silicide as opposed to highly doped silicon in conventional devices.The aim is to improve the on current and reduce the leakage current of the low gate length devices. It is shown that, the doped extension regions adjacent to the source/drain schottky barrier improves the drive current by shrinking the schottky barrier and also the simulation results shows that the increasing doping levels at the source/drain(S/D) extensions increases the leakage current. The optimized device shows excellent short channel immunity, compared to conventional CMOS devices. Thus the optimal S/D design for high performance is more likely to be decided by practical considerations such as process integration. The analysis also shows that, the best characteristics of the proposed device can be obtained only if using proper silicides at the S/D regions. This paper presents the simulation study of ESD-ST-SOIFET. The silicide technology can be used for the fabrication of this device. This device is considered one of the most promising candidates for future nanotechnology world.

Keywords

Contact Resistance, High-K Gate Dielectrics, Nano Scale Devices, Semiconductor Device Modeling.

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D. Jackuline Moni ¹, B. Suresh ¹, R. Malarkodi ¹

Affiliations
1 Karunya University, IN

Abstract

This paper describes the device characteristics verification and biasing analysis of Silicon on Insulator (SOI) devices with single gate and double gate in comparison with bulk MOSFET. Improvement in threshold voltage controllability and variability has been observed for these devices. One of the leading double gate devices, FinFET is analyzed over different parameter variations and with back biasing techniques. Wide threshold voltage controllability of the FinFET device in comparison with all other devices is justified. The performance of independently gated four–terminal FinFETs with symmetric gate-oxide thickness (tox1=tox2=0.5nm) and the same kind FinFET with asymmetric gate-oxide thickness whose front gate-oxide tox1=0.5nm and back gate-oxide tox2=5nm, has been successfully analyzed. A comparison between symmetric and asymmetric gate work function has been analyzed. Also the gate oxide materials are changed and the response for High-K materials is analyzed and compared with the conventional devices. Some of the peculiar characteristics exhibited by the device for the fin width variation when controlled in single gate (SG) and independent gate (IG) modes have been proposed here.

Keywords

FinFET, SOI, Single Gate, Double Gate, High k.

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