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Udhayakumar, A.
- Multi-Party Electronic Payment System Using ECCMA Algorithm
Authors
1 Dept. of Computer Science, Karpagam University, Coimbatore, IN
2 Dept. of Computer Science, Tamil University, Thanjavur-613010, Tamil Nadu, IN
Source
Networking and Communication Engineering, Vol 6, No 8 (2014), Pagination: 328-334Abstract
Security in digital communications nowadays depends on cryptography. Multiparty Key Access depends on algorithms for generating asymmetric keys. The present algorithmic rule in use is MKA that uses mathematical properties of prime numbers and therefore the quality of resolving giant numbers to come up with secure asymmetric keys. A more modern algorithmic rule that might be used is Elliptic Curve Cryptography (ECC). Elliptic Curves have mathematical properties in which specified uneven keys is generated which is stronger than those created by Existing strategies. To investigate the utilization of ECC for MKA, a basic ECC generator is used and it will generate live keys and coding durations. The comparative key strength of ECC and Existing strategies is taken into thought; ECC is orders of magnitude quicker than Existing strategies for a similar security. The problems preventing the adoption of ECC using MKA in Cryptography area for raising security unit mentioned. The properties rights of ECC are utilized in MKA, the biggest obstacle to ECC adoption are substitution the present MKA infrastructure that uses Existing strategies. It is expected that ECC in MKA can become customary by 2020.Keywords
Cryptography, Decryption, Encryption, Elliptic Curve, Multi-Party.
- Performance Analysis for Electronic Payment Systems
Authors
1 Tamil University, Thanjavur, IN
2 Karpagam University, Coimbatore, IN
3 AM Jain College, Chennai, IN
Source
Networking and Communication Engineering, Vol 4, No 13 (2012), Pagination: 800-802Abstract
In this paper, thus the research analysis, design and implementation phase has been described for our research. It is proposed framework architecture for the Secure Multiparty Electronic Payments in mobile computing in order to support self-protection in AmI scenarios. The architecture of our framework is device-and platform independent and focuses on the use of auctions protocols for electronic payments policies. The top priority was the security of the auctions. All secret information that is exchanged between the auctions host and the peers is encrypted and protected against illegitimate modifications. it will extend the modularity of the proposed framework in order to allow individual utility functions and a replaceable module for determining the winning policy. Further, the integration of our framework into the refinement process of semantic high-level policies is in progress.Keywords
Multi-party Security, Mobile Computing, Cryptography, Negotiation.- Closed Form Expression for Low Voltage Using Power Gating CCMOS (Clocked CMOS) D-Flip Flop
Authors
Source
Fuzzy Systems, Vol 10, No 7 (2018), Pagination: 165-167Abstract
In Advanced computing system High speed, power is important parameter to be considered in designing a system. In this paper, we proposed the CCMOS (Clocked CMOS) with fixed frequency and throughput.
The average power consumption using power gating CCMOS is low compared to conventional CMOS logic. The dissipation of power in CCMOS logic can be minimized. The energy consumption by CCMOS logic for various types of D-flip flops and their static and average powers are computed. We compares various types of flip flops in terms of power. From the simulation results, the total power of CMOS and CCMOS are calculated and compared. The circuits have been simulated. It has high speed. It has minimum power consumption compared with all other realizations.
Keywords
Component, Formatting, Style, Styling, Insert. (Keywords)- A Closed Form Expression for Low Power Voltage Using Power Gating CCMOS (Clocked CMOS) D Flip Flop
Authors
Source
Programmable Device Circuits and Systems, Vol 10, No 7 (2018), Pagination: 130-135Abstract
In Advanced computing system high speed, power is important parameter to be considered in designing a system. In this paper, we proposed the CCMOS (Clocked CMOS) with fixed frequency and throughput.
The average power consumption using power gating CCMOS is low compared to conventional CMOS logic. The dissipation of power in CCMOS logic can be minimized. The energy consumption by CCMOS logic for various types of D-flip flops and their static and average powers are computed. We compares various types of flip flops in terms of power. From the simulation results, the total power of CMOS and CCMOS are calculated and compared. The circuits have been simulated. It has high speed. It has minimum power consumption compared with all other realizations.