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Prathiba, A.
- Design and Implementation of a Generic CORDIC Processor and its Application as a Waveform Generator
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Authors
Affiliations
1 School of Electronics Engineering, VIT University Chennai Campus, Chennai-600127, Tamil Nadu, IN
2 NXP Semiconductors India PVT LTD, Bangalore-560045, Karnataka, IN
1 School of Electronics Engineering, VIT University Chennai Campus, Chennai-600127, Tamil Nadu, IN
2 NXP Semiconductors India PVT LTD, Bangalore-560045, Karnataka, IN
Source
Indian Journal of Science and Technology, Vol 8, No 19 (2015), Pagination:Abstract
Background: With the advent in hand held mobile computing devices, the demand for high performance compact processors is increasing. In this work a processor is designed with hardwired instructions for elementary mathematical functions like sine, cosine, sinh, cosh, division and multiplication. Methods: The processor employs Coordinate Rotation Digital Computer (CORDIC) algorithm for efficient hardware implementation of the above mentioned instructions. The parallel and pipelined implementation of the processor is carried out. The pipelined processor is configured as waveform generator. The novelty of this work is the integration of both trigonometric and hyperbolic operations in the same processor. Findings: ASIC Implementation is carried out with 40nm technology libraries. The parallel processor so designed operates at maximum frequency of 24.23 MHz and pipelined processor operates at maximum frequency of 261.36 MHz. Conclusion: This increase in operating frequency is achieved at the cost of increased silicon area and optimal power dissipation. The waveform generator generates sine, cosine waves of 3.5 MHz and sine hyperbolic, cosine hyperbolic waves and exponential waves of 7.9 MHz. The limitation being the waveform generator generates waves of constant frequency. Additional circuit is required in generating waves of different frequencies.Keywords
Coordinate Rotation Digital Computer (CORDIC), Parallel Architecture, Pipelined Architecture, Waveform Generator- FPGA Implementation and Analysis of the Block Cipher Mode Architectures for the PRESENT Light Weight Encryption Algorithm
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Authors
Affiliations
1 School of Electronics Engineering, VIT University Chennai, Chennai - 600127, IN
1 School of Electronics Engineering, VIT University Chennai, Chennai - 600127, IN
Source
Indian Journal of Science and Technology, Vol 9, No 38 (2016), Pagination:Abstract
Objective: This paper presents the Field Programmable Gate Array (FPGA) implementations of the different block cipher mode architectures of the ISO standardized light weight block cipher PRESENT, designed for resource constrained devices. Methods/ Statistical Analysis: The performance evaluations compare the implementations of the different block cipher modes, namely Electronic Code Book (ECB) mode, Cipher Block Chaining (CBC) mode, Cipher Feedback Mode (CFB), Output Feed Back Mode (OFB) and CounTeR (CTR) mode for the PRESENT cipher. The throughput of encryption of three successive 64 bit blocks of data ranges from 565.312Mbps to 574.784Mbps for the modes other than the cipher feedback mode in the Spartan-3 FPGA. The throughput for providing confidentiality through encryption in the cipher feedback mode arrives as 68.912 Mbps, 155.392Mbps and 300.8 Mbps for a 64 bit block of data for the input streams of size 8 bits, 16 bits and 32 bits respectively. Findings: The throughput of the block cipher mode hardware architectures of the light weight cipher PRESENT demonstrates the high speed performance of the cipher in encryption/decryption of data as blocks and streams. Application/ Improvement: The significance of the proposed work is to know the hardware performance of the different modes of operation for the light weight block cipher PRESENT. The performance estimation of the block cipher modes operations of the PRESENT cipher definition in hardware have been carried out for the first time.Keywords
Block Cipher Modes, FPGA, Internet of Things (IoT), Light Weight Cipher.- Cultivation, Composting, Biochemical and Molecular Characterization of Pleurotus platypus (Cooke and Massee) Sacc
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Authors
Affiliations
1 Department of Botany and Microbiology, A. V. V. M Sri Pushpam College, Poondi – 613 503, Thanjavur District, Tamil Nadu, IN
2 Department of Botany and Microbiology, A. V. V. M Sri Pushpam College, Poondi – 613 503, Thanjavur District, Tamil Nadu., IN
1 Department of Botany and Microbiology, A. V. V. M Sri Pushpam College, Poondi – 613 503, Thanjavur District, Tamil Nadu, IN
2 Department of Botany and Microbiology, A. V. V. M Sri Pushpam College, Poondi – 613 503, Thanjavur District, Tamil Nadu., IN