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A Processor-Sharing Scheduling Strategy for NFV Nodes


Affiliations
1 Dipartimento di Ingegneria Elettrica, Elettronica e Informatica (DIEEI), University of Catania, 95123 Catania, Italy
 

The introduction of the two paradigms SDN and NFV to "softwarize" the current Internet is making management and resource allocation two key challenges in the evolution towards the Future Internet. In this context, this paper proposes Network-Aware Round Robin (NARR), a processor-sharing strategy, to reduce delays in traversing SDN/NFV nodes. The application of NARR alleviates the job of the Orchestrator by automatically working at the intranode level, dynamically assigning the processor slices to the virtual network functions (VNFs) according to the state of the queues associated with the output links of the network interface cards (NICs). An extensive simulation set is presented to show the improvements achieved with respect to two more processorsharing strategies chosen as reference.
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  • A Processor-Sharing Scheduling Strategy for NFV Nodes

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Authors

Giuseppe Faraci
Dipartimento di Ingegneria Elettrica, Elettronica e Informatica (DIEEI), University of Catania, 95123 Catania, Italy
Alfio Lombardo
Dipartimento di Ingegneria Elettrica, Elettronica e Informatica (DIEEI), University of Catania, 95123 Catania, Italy
Giovanni Schembra
Dipartimento di Ingegneria Elettrica, Elettronica e Informatica (DIEEI), University of Catania, 95123 Catania, Italy

Abstract


The introduction of the two paradigms SDN and NFV to "softwarize" the current Internet is making management and resource allocation two key challenges in the evolution towards the Future Internet. In this context, this paper proposes Network-Aware Round Robin (NARR), a processor-sharing strategy, to reduce delays in traversing SDN/NFV nodes. The application of NARR alleviates the job of the Orchestrator by automatically working at the intranode level, dynamically assigning the processor slices to the virtual network functions (VNFs) according to the state of the queues associated with the output links of the network interface cards (NICs). An extensive simulation set is presented to show the improvements achieved with respect to two more processorsharing strategies chosen as reference.