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Authors
Affiliations
1 Department of VLSI, Sasurie Academy of
Engineering, IN
Source
Digital Signal Processing, Vol 4, No 10 (2012), Pagination: 432-436
Abstract
Low power VLSI circuits have become important criteria for designing the energy efficient electronic designs for high performance and portable devices .The multipliers are the main key structure for designing an energy efficient processor where a multiplier design decides the digital signal processors efficiency. In this paper, 4*4 Wallace tree multiplier architecture is being designed by using 1-bit full adders following various logic styles. The full adders have been designed using various logic styles following a unique pattern of structure to improve their performance in various means like less transistors, low power, minimal delay, reduced area and increased power delay product. The various types of adders used in our paper are complementary mosfet (CMOS) style, double-pass transistor (DPL) style, swing-restored complementary (SR-CPL) pass logic style. The main objective of our work is to calculate the average power, delay and power delay product of various 1-bit full adders following various logic styles at 2.5v supply voltage with Vmin of 0v at 25c temperature with 6.00μm technology and simulating them with DSCH2 of Microwind tool. An Wallace tree multiplier architecture is designed using full adder structure alone and then the above said various full adder logic style adders are replaced in the multiplier architecture and then their outputs are generated, such that their average power are calculated.
Keywords
Area, Delay, Full Adder, Logic Styles, Average Power.
