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Authors
Affiliations
1 SET, Jain University, Bangalore, IN
2 7 Star Technologies, Bangalore, IN
3 Allied Tools and Electronics, Bangalore, IN
4 Signal Processing and VLSI, SET, Jain University, Bangalore, IN
Source
International Journal of Scientific Engineering and Technology, Vol 1, No 5 (2012), Pagination: 207-208
Abstract
In this paper, VHDL & functional analysis is used to model and to study the effect of faults on gate level circuits respectively. The model is developed via abstraction of industry standard single stuck line (SSL) faults into the behavioral domain and the effects of these faults on gate level circuits are discussed.
Keywords
Fault Models, Behavioral Modeling, VHDL, Functional Analysis, RTL Synthesis, Stuck Faults.
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