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A Review of Processor Architectures


Affiliations
1 Dept. of Electronics and Communication Engg, SET, Jain University, Jakkasandra, Bangalore., India
2 Dept. of Electronics and Communication Engineering, SET, Jain University, Bangalore., India
3 7 Star Technologies, Bangalore., India
     

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In this paper, a brief review of the processor architectures has been presented. The paper starts from the Non-Von Neumann model and discusses on the possible next generation computer architectures.
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  • Proc.Caltech Conf.VLSI, C.Seitz, ed., Jan.1979.

  • Proc. VLSI 81, J.P Gray, ed., Academic Press, New York, 1981.

  • Proc. Int’l Conf. Fifth Generation Computer Systems, Japan Information Processing Center, Oct. 1981.

  • “Interim Report on the syudy and Research on Fifth Generation Computers,” Japan Information Processing Development Center, 1980.

  • M.J Foster and H.T Kung, “The Design of Special Purpose VLSI Chips” computer, Vol.13, No. 1, Jan 1980, pp. 26-40.

  • D.A Patterson and C.H Sequin, “RISC I: A Reduced Instruction Set VLSI Computer,” Proc. Eighth Int’l Symp. Computer Architecture, May 1981, pp. 443-457.

  • D.A patterson and D.R Ditzel, “The case for the Reduced Instruction Set Computer,” Computer Archtecture News, Vol. 8, No.6 Oct, 1980, pp.25-32.

  • D.A Patterson and C.H Sequin, “RISC I: A Reduced Instruction Set VLSI Computer,” Proc. Eighth Int’l Symp. Computer Architecture, May 1981, pp. 443-457.

  • D.T Fitzpatrick etal., “A RISCy Approach to VLSI,” VLSI Design, 4th QTR. 1981, pp. 14-20.

  • J. Holloway etal., “Scheme 79 Chip” MIT AI Memo 559, Cambridge, Mass., Jan.1980.

  • G.J. Sussaman et al., “Scheme -79 LISP on a Chip” Computer, Vol. 14., No.7, July 1981, pp.10-21.

  • S. A Browning and C. L Seitz, “Communication in a tree Machine” Proc. Caltech Conf., VLSI, Jan 1981.

  • A.M. Desoain and D. A patterson, “X Tree: A tree Structured Multiprocessor Computer Architecture” Proc. Fifth Int’l Symp, Computer Architecture, Apr. 1978, pp. 144-151.

  • D. A patterson et al., “ Design Considerations for the VLSI processor of X-Tree” Proc sixth Int’l Symp, Computer Architecture, Apr. 1979, pp. 90-100.

  • S.A Browning, “The Tree Machine: A Highly Concurrent Computiong Environment” PhD Dissertation, Department of Computer Science, Caltech, 1980.

  • J.L Bently and H.T Kung, “Two Papers on a tree structured parallel computer”, Technical report CMU CS-79-142.

  • G.A Mago, “A Cellular Computer Architecture for functional

  • Programming”, Proc, Compcon spring 80 pp 179-185.

  • Arvind et al., “A processing element for a large multiple processor dataflow machine” Proc. Int’l Conf. Circuits and computers, oct.1980.

  • A.L Davis, “A data driven machine architecture suitable for VLSI implementation” proc. Caltech conf. VLSI Jan.19 79, pp.479-494.

  • J.B Dennis, “Data flow super computers” computer, Vol.13, No.11, Nov.1980, pp.48-56.

  • Yingbiao Y, Jianwu .Z, “Survey on Microprocessor Architecture and Development Trends”, IEEE International Conference on Communication Technology Proceedings, 11th, 2008.


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  • A Review of Processor Architectures

Abstract Views: 446  |  PDF Views: 2

Authors

V. Amritha Mulay
Dept. of Electronics and Communication Engg, SET, Jain University, Jakkasandra, Bangalore., India
Anoop S. Shandilya
Dept. of Electronics and Communication Engineering, SET, Jain University, Bangalore., India
Mujeeb Ulla Jeelani
7 Star Technologies, Bangalore., India
N. Venkatesh Kumar
Dept. of Electronics and Communication Engg, SET, Jain University, Jakkasandra, Bangalore., India

Abstract


In this paper, a brief review of the processor architectures has been presented. The paper starts from the Non-Von Neumann model and discusses on the possible next generation computer architectures.

References