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Low Latency Prefix Accumulation Driven Compound MAC Unit for Efficient FIR Filter Implementation


Affiliations
1 Department of ECE, Jawaharlal Nehru Technological University Ananthapur, Ananthapuram, India
2 Department of ECE, SVU College of Engineering, Sri Venkateswara University, Tirupati, India
 

This article presents hierarchical single compound adder-based MAC with assertion based error correction for speculation variations in the prefix addition for FIR filter design. The VLSI implementation of approximation in prefix adder results show a significant delay and complexity reductions, all this at the cost of latency measures when speculation fails during carry propagation, which is the main reason preventing the use of speculation in parallel-prefix adders in DSP applications. The speculative adder which is based on Han Carlson parallel prefix adder structure accomplishes better reduction in latency. Introducing a structured and efficient shift-add technique and explore latency reduction by incorporating approximation in addition. The improvements made in terms of reduction in latency and merits in performance by the proposed MAC unit are showed through the synthesis done by FPGA hardware. Results show that proposed method outpaces both formerly projected MAC designs using multiplication methods for attaining high speed.

Keywords

Multiply Accumulate (MAC) Unit, Distributed Arithmetic, Fir Filter, Compound Adder.
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  • Low Latency Prefix Accumulation Driven Compound MAC Unit for Efficient FIR Filter Implementation

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Authors

G. Reddy Hemantha
Department of ECE, Jawaharlal Nehru Technological University Ananthapur, Ananthapuram, India
S. Varadarajan
Department of ECE, SVU College of Engineering, Sri Venkateswara University, Tirupati, India
M. N. Giriprasad
Department of ECE, Jawaharlal Nehru Technological University Ananthapur, Ananthapuram, India

Abstract


This article presents hierarchical single compound adder-based MAC with assertion based error correction for speculation variations in the prefix addition for FIR filter design. The VLSI implementation of approximation in prefix adder results show a significant delay and complexity reductions, all this at the cost of latency measures when speculation fails during carry propagation, which is the main reason preventing the use of speculation in parallel-prefix adders in DSP applications. The speculative adder which is based on Han Carlson parallel prefix adder structure accomplishes better reduction in latency. Introducing a structured and efficient shift-add technique and explore latency reduction by incorporating approximation in addition. The improvements made in terms of reduction in latency and merits in performance by the proposed MAC unit are showed through the synthesis done by FPGA hardware. Results show that proposed method outpaces both formerly projected MAC designs using multiplication methods for attaining high speed.

Keywords


Multiply Accumulate (MAC) Unit, Distributed Arithmetic, Fir Filter, Compound Adder.

References