ICTACT Journal on Microelectronics

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Power Efficient High Speed Adaptive Biased Operational Amplifier


Affiliations
1 Department of Electronics and Communication Engineering, Indira Gandhi Delhi Technical University for Women, India
     

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This paper presents a new adaptive biasing technique for improving the slew rate of CMOS opamps without increasing the power consumption. All the proposed circuits for adaptive biasing are implemented using a current subtractor and NMOS based circuit. Further, the input stage of opamp in proposed circuits were substituted by Flipped Voltage Follower circuit and Self Cascode structure to study their effects on adaptive biasing circuits. The conclusion of this work is that there is a notable enhancement in slew rate, settling time and power dissipation in proposed adaptive biasing techniques. All the circuits have been designed using 180nm CMOS technology and simulated using cadence virtuoso.

Keywords

Adaptive Biasing, Opamp, Slew Rate, Flipped Voltage Follower, Self Cascode, Power Dissipation.
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  • Power Efficient High Speed Adaptive Biased Operational Amplifier

Abstract Views: 237  |  PDF Views: 0

Authors

Nimeesha
Department of Electronics and Communication Engineering, Indira Gandhi Delhi Technical University for Women, India
Shikha Soni
Department of Electronics and Communication Engineering, Indira Gandhi Delhi Technical University for Women, India
Vandana Niranjan
Department of Electronics and Communication Engineering, Indira Gandhi Delhi Technical University for Women, India
Ashwni Kumar
Department of Electronics and Communication Engineering, Indira Gandhi Delhi Technical University for Women, India

Abstract


This paper presents a new adaptive biasing technique for improving the slew rate of CMOS opamps without increasing the power consumption. All the proposed circuits for adaptive biasing are implemented using a current subtractor and NMOS based circuit. Further, the input stage of opamp in proposed circuits were substituted by Flipped Voltage Follower circuit and Self Cascode structure to study their effects on adaptive biasing circuits. The conclusion of this work is that there is a notable enhancement in slew rate, settling time and power dissipation in proposed adaptive biasing techniques. All the circuits have been designed using 180nm CMOS technology and simulated using cadence virtuoso.

Keywords


Adaptive Biasing, Opamp, Slew Rate, Flipped Voltage Follower, Self Cascode, Power Dissipation.

References