Open Access Subscription Access
Open Access Subscription Access
Analysis of Energy Efficient Two Level Cache Using Counting Bloom Filter
The microprocessor system’s Caches consume much of a power and energy consumption. In this paper, a set associative cache system and way tagged L2 cache and way tagged L2 cache with counting bloom filter caches are compared. The tagged cache beyond continue the method tag of level two cache in the level one cache for the duration of understand writing process, this process prepare level two cache towards operate within a corresponding map in absolute process in the time of write hits that results in mainstream of the level two cache access. Here CBFs are proposed in the way tagged L2 cache to recover the energy and swiftness of membership tests by maintain a vague and compact demonstration of a large set to be searched. Designs were developed using behavioural VHDL and synthesized in Xilinx 8.1 Spartan 2E device. Experimental results were showing that the future way tagged L2 cache with CBF consumes lesser 50% of power than the set associative cache systems.
CDF, Energy And Power, Set Associative Cache, Way Tagged L2 Cache.
- J. Dai, and L. Wang, “Way-tagged cache: An energy-efficient L2 cache architecture under write write-through policy,” in Proceedings of the 2009 International Symposium on Low Power Electronics and Design (ISLPED), pp. 159-164, 2009.
- E. Safi, A. Moshovos, and A. Veneris, “L-CBF: A low-power, fast counting bloom filter architecture,” IEEE Transactions on Very Large Scale Integration Systems, vol. 16, no. 6, pp. 628-638, July 2008.
- S. Kiruthika, R. N. Kumar, and S. Valarmathy, “Comparative analysis of 4-bit multipliers using low power 8-transistor full adder cells,” International Journal of Emerging Technology and Advanced Engineering (IJETAE), vol. 3, no. 1, January 2013.
- S. G. Siddharth, M. Ramkumar, and S. Kiruthika, “Railway track scanning and surveillance robot using wireless technology,” Journal of Harmonized Research in Engineering (JOHR), vol. 2, no. 1, pp. 194-200, 2014.
- S. Kiruthika, and A. V. Starbino, “Design and analysis of FIR filters using low power multiplier and full adder cells,” 2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE), pp. 1-5, IEEE, 2017.
- S. Kiruthika, and B. Balraj, “Design of 4x4 wallace tree multiplier based on 0.12μm CMOS technology using GDI full adder,” International Journal of Pure and Applied Mathematics, vol. 119, no. 15 (sp. issue), pp. 3293-3300, 2018.
- P. Sakthi, S. Maheswari, and P. Yuvarani, “High performance vedic multiplier using compressors,” International Journal of Applied Engineering Research, vol. 10, no. 20, pp. 16882-16886, 2015.
- P. Sakthi, and P. Yuvarani, “Multipliers based on Urdhva Tiryagbhyam algorithm: A survey,” Advances in Natural and Applied Sciences, vol. 8, no. 19, pp. 100-106, 2014.
- D. Brooks, V. Tiwari, and M. Martonosi, “Wattch: A framework for architectural level power analysis and optimizations,” in Proceedings of the 27th International Symposium on Computer Architecture, pp. 83-94, Vancouver, BC, June 2000.
- S. Wilton, and N. Jouppi, “An enhanced access and cycle time model for on-chip caches,” 1994.
- M. R. Stan, A. F. Tenca, and M. D. Ercegovac, “Long and fastvup/down counters,” IEEE Transactions on Computers, vol. 47, no. 7, pp. 722-735, July 1998.
Abstract Views: 31
PDF Views: 1