A Comparative Analysis of Low Power D Flip Flop Using Leakage Power Reduction Techniques

This paper proposes a new topology to low power approaches for very large scale integration (VLSI) design. Power dissipation is one of the major concerns when designing a VLSI system. Until recently, dynamic power was the only concern. However, as the technology feature size shrinks, static power, which was negligible before, becomes an issue as important as dynamic power. Since static power increases dramatically in nanoscale silicon VLSI technology, the importance of reducing leakage. This paper describes a low-leakage technique. We are doing comparable analysis of different low power, leakage current reduction techniques like SLEEP approach, STACK, SLEEPY–STACK, SLEEPY KEEPER, SLEEPY–STACK with KEEPER, LEAKAGE FEEDBACK and LEAKAGE FEEDBACK with STACK techniques. Which reduces leakage power while saving exact logic state. Based on simulation results a conventional D Flip flop with the Full sleep approach achieves up to 95 % less power consumption.